About me

I am a Ph.D. student studying computer architecture in Berkeley Architecture Reseach, as part of the ADEPT Lab, advised by Krste Asanović.

A list of open-source projects I have developed:

• The Berkeley Out-of-Order Machine, a high-performance super-scalar out-of-order RISC-V processor
• Chipyard, a RISC-V SoC design framework
• Constellation, a Chisel network-on-chip generator
• ReRoCC, a accelerator disaggregation interface and programming model
• Shuttle, a area-efficient dual-issue RISC-V processor
• Saturn, a compliant compact RISC-V vector unit

I also contribute to

• RocketChip, a library of Chisel generators for RISC-V SoCs
• Spike, a RISC-V functional ISA simulator
• Gemmini, a systolic-array machine-learning accelerator

My Google Scholar.