Jerry Zhao — About Me

Current Role

Computer Architect at OpenAI.
Based in Oakland, California.
At OpenAI, I work on hardware design.

Education

Ph.D. student at UC Berkeley (2019–2025) in the SLICE, ADEPT, and ASPIRE labs.
Advisors: Krste Asanović and Borivoje Nikolić.
B.S. in Electrical Engineering and Computer Science (2019).

Research Focus

Computer architecture and microarchitecture.
Performance modeling, accelerator design, and hardware design methodologies.
Involved in numerous tapeouts.

Industry Experience

Interned at Apple in 2021 and 2022:
- Platform Architecture CPU team.
- Vector and Numerics team.

Technical Expertise

CPU microarchitecture, vector microarchitecture, AI microarchitecture.
RTL design, simulation, performance modeling.
Hardware design methodology, VLSI flows.
RISC‑V, Chisel, Rust.
Network‑on‑chip design, SoC design.

Project Overview

I have contributed to a wide range of architecture and hardware projects. My work includes deep superscalar out‑of‑order cores (BOOM, SonicBOOM), machine learning accelerators (GEMMINI), vector units (Saturn), interconnects (Constellation), and SoC design frameworks (Chipyard). I am deeply familiar with DSL‑based hardware design flows, performance modeling, architecture design, and accelerator ISA design.

SonicBOOM (Lead developer)

Repo: riscv-boom/riscv-boom
Description: Extends the Berkeley Out‑of‑Order Machine (BOOM) to significantly higher performance by pushing aggressive superscalar out‑of‑order techniques into an open‑source RISC‑V core.
Focus areas: Innovations in fetch, rename, scheduling, and execution to sustain wide‑issue pipelines and deep speculation; modular, extensible Chisel‑based design.
Key improvements: Enhanced branch prediction; wider instruction issue and commit; refined load–store queues; scalable instruction scheduling and register renaming structures.
Notable: At one point the fastest RISC‑V processor; exposed Linux bugs hidden by deep speculation; first open‑source implementation of the industry‑standard TAGE branch predictor.

GEMMINI (RTL developer)

Repo: ucb-bar/gemmini
Description: Parameterizable open‑source systolic‑array accelerator for dense linear algebra and ML workloads, part of the RISC‑V ecosystem.
Contributions: Physical‑design friendly features, including banking of the local memory system.

Saturn (Lead developer)

Repo: ucb-bar/saturn-vectors
Description: Research vector processor for AI and HPC workloads; fully RVV 1.0 compliant with support for virtual memory and precise faults.
Microarchitecture: Out‑of‑order execution, vector chaining, and load/store decoupling.

Constellation (Lead developer)

Repo: ucb-bar/constellation
Description: Open‑source network‑on‑chip generator for scalable on‑chip interconnects in RISC‑V SoCs.

Chipyard (Lead developer)

Repo: ucb-bar/chipyard
Description: Open‑source SoC design framework integrating cores, accelerators, memory systems, and I/O with RTL simulation, FPGA prototyping, and ASIC flows.